{"schema":"libjg2-1", "vpath":"/git/", "avatar":"/git/avatar/", "alang":"", "gen_ut":1747285316, "reponame":"openssl", "desc":"OpenSSL", "owner": { "name": "Andy Green", "email": "andy@warmcat.com", "md5": "c50933ca2aa61e0fe2c43d46bb6b59cb" },"url":"https://warmcat.com/repo/openssl", "f":3, "items": [ {"schema":"libjg2-1", "cid":"e143c951be991aa78c04a31f634f215d", "commit": {"type":"commit", "time": 1521456453, "time_ofs": 60, "oid_tree": { "oid": "fbaf90d1479545cdaf21c673e8128ec3798527cb", "alias": []}, "oid":{ "oid": "51cf8ba038aae10df9895b0001715938f7ad0c75", "alias": []}, "msg": "engines/asm/e_padlock*: add support for Zhaoxin's x86 platform", "sig_commit": { "git_time": { "time": 1521456453, "offset": 60 }, "name": "Andy Polyakov", "email": "appro@openssl.org", "md5": "50bd64fa2a792cbbf679fa16213a3b2a" }, "sig_author": { "git_time": { "time": 1521180916, "offset": 480 }, "name": "JeffZhao", "email": "jeffzhao@zhaoxin.com", "md5": "22f1997dcdfad8ac68f468d37dca8841" }}, "body": "engines/asm/e_padlock*: add support for Zhaoxin's x86 platform\n\nVIA and Shanghai United Investment Co.,Ltd. found Shanghai ZhaoXin,\nwhich is a fabless x86 CPU IC design company. ZhaoXin has issued\nZX-C, ZX-D x86 processors, which have 'Shanghai' CPU vendor id.\n\nReviewed-by: Andy Polyakov \u003cappro@openssl.org\u003e\nReviewed-by: Matt Caswell \u003cmatt@openssl.org\u003e\n(Merged from https://github.com/openssl/openssl/pull/5640)\n" , "diff": "diff --git a/engines/asm/e_padlock-x86.pl b/engines/asm/e_padlock-x86.pl\nindex c4129e8..0cea549 100644\n--- a/engines/asm/e_padlock-x86.pl\n+++ b/engines/asm/e_padlock-x86.pl\n@@ -73,11 +73,20 @@ $chunk\u003d\u0022ebx\u0022;\n \t\u0026cpuid\t();\n \t\u0026xor\t(\u0022eax\u0022,\u0022eax\u0022);\n \t\u0026cmp\t(\u0022ebx\u0022,\u00220x\u0022.unpack(\u0022H*\u0022,'tneC'));\n-\t\u0026jne\t(\u0026label(\u0022noluck\u0022));\n+\t\u0026jne\t(\u0026label(\u0022zhaoxin\u0022));\n \t\u0026cmp\t(\u0022edx\u0022,\u00220x\u0022.unpack(\u0022H*\u0022,'Hrua'));\n \t\u0026jne\t(\u0026label(\u0022noluck\u0022));\n \t\u0026cmp\t(\u0022ecx\u0022,\u00220x\u0022.unpack(\u0022H*\u0022,'slua'));\n \t\u0026jne\t(\u0026label(\u0022noluck\u0022));\n+\t\u0026jmp\t(\u0026label(\u0022zhaoxinEnd\u0022));\n+\u0026set_label(\u0022zhaoxin\u0022);\n+\t\u0026cmp\t(\u0022ebx\u0022,\u00220x\u0022.unpack(\u0022H*\u0022,'hS '));\n+\t\u0026jne\t(\u0026label(\u0022noluck\u0022));\n+\t\u0026cmp\t(\u0022edx\u0022,\u00220x\u0022.unpack(\u0022H*\u0022,'hgna'));\n+\t\u0026jne\t(\u0026label(\u0022noluck\u0022));\n+\t\u0026cmp\t(\u0022ecx\u0022,\u00220x\u0022.unpack(\u0022H*\u0022,' ia'));\n+\t\u0026jne\t(\u0026label(\u0022noluck\u0022));\n+\u0026set_label(\u0022zhaoxinEnd\u0022);\n \t\u0026mov\t(\u0022eax\u0022,0xC0000000);\n \t\u0026cpuid\t();\n \t\u0026mov\t(\u0022edx\u0022,\u0022eax\u0022);\ndiff --git a/engines/asm/e_padlock-x86_64.pl b/engines/asm/e_padlock-x86_64.pl\nindex 834b1ea..9eff881 100644\n--- a/engines/asm/e_padlock-x86_64.pl\n+++ b/engines/asm/e_padlock-x86_64.pl\n@@ -57,11 +57,20 @@ padlock_capability:\n \tcpuid\n \txor\t%eax,%eax\n \tcmp\t\u005c$`\u00220x\u0022.unpack(\u0022H*\u0022,'tneC')`,%ebx\n-\tjne\t.Lnoluck\n+\tjne\t.Lzhaoxin\n \tcmp\t\u005c$`\u00220x\u0022.unpack(\u0022H*\u0022,'Hrua')`,%edx\n \tjne\t.Lnoluck\n \tcmp\t\u005c$`\u00220x\u0022.unpack(\u0022H*\u0022,'slua')`,%ecx\n \tjne\t.Lnoluck\n+\tjmp\t.LzhaoxinEnd\n+.Lzhaoxin:\n+\tcmp\t\u005c$`\u00220x\u0022.unpack(\u0022H*\u0022,'hS ')`,%ebx\n+\tjne\t.Lnoluck\n+\tcmp\t\u005c$`\u00220x\u0022.unpack(\u0022H*\u0022,'hgna')`,%edx\n+\tjne\t.Lnoluck\n+\tcmp\t\u005c$`\u00220x\u0022.unpack(\u0022H*\u0022,' ia')`,%ecx\n+\tjne\t.Lnoluck\n+.LzhaoxinEnd:\n \tmov\t\u005c$0xC0000000,%eax\n \tcpuid\n \tmov\t%eax,%edx\n","s":{"c":1747285316,"u": 38082}} ],"g": 38813,"chitpc": 0,"ehitpc": 0,"indexed":0 , "ab": 0, "si": 0, "db":0, "di":0, "sat":0, "lfc": "0000"}