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{"schema":"libjg2-1",
"vpath":"/git/",
"avatar":"/git/avatar/",
"alang":"",
"gen_ut":1753167256,
"reponame":"openssl",
"desc":"OpenSSL",
"owner": { "name": "Andy Green", "email": "andy@warmcat.com", "md5": "c50933ca2aa61e0fe2c43d46bb6b59cb" },"url":"https://warmcat.com/repo/openssl",
"f":3,
"items": [
{"schema":"libjg2-1",
"cid":"a85bdf2ecf5eaed3fffc2f14464b5d33",
"commit": {"type":"commit",
"time": 1511643970,
"time_ofs": 60,
"oid_tree": { "oid": "7aaeff23531ff295f6803e1857c1e5c7f2bb32ce", "alias": []},
"oid":{ "oid": "a8f302e5bae18ce129b81a3f7a5f3ea7f9785ca1", "alias": []},
"msg": "poly1305/asm/poly1305-x86_64.pl: switch to pure AVX512F.",
"sig_commit": { "git_time": { "time": 1511643970, "offset": 60 }, "name": "Andy Polyakov", "email": "appro@openssl.org", "md5": "50bd64fa2a792cbbf679fa16213a3b2a" },
"sig_author": { "git_time": { "time": 1511169854, "offset": 60 }, "name": "Andy Polyakov", "email": "appro@openssl.org", "md5": "50bd64fa2a792cbbf679fa16213a3b2a" }},
"body": "poly1305/asm/poly1305-x86_64.pl: switch to pure AVX512F.\n\nConvert AVX512F+VL+BW code path to pure AVX512F, so that it can be\nexecuted even on Knights Landing. Trigger for modification was\nobservation that AVX512 code paths can negatively affect overall\nSkylake-X system performance. Since we are likely to suppress\nAVX512F capability flag [at least on Skylake-X], conversion serves\nas kind of \u0022investment protection\u0022.\n\nReviewed-by: Rich Salz \u003crsalz@openssl.org\u003e\n(Merged from https://github.com/openssl/openssl/pull/4758)\n"
,
"diff": "diff --git a/crypto/poly1305/asm/poly1305-x86_64.pl b/crypto/poly1305/asm/poly1305-x86_64.pl\nindex 4482d39..4519084 100755\n--- a/crypto/poly1305/asm/poly1305-x86_64.pl\n+++ b/crypto/poly1305/asm/poly1305-x86_64.pl\n@@ -24,6 +24,16 @@\n #\n # Add AVX512F+VL+BW code path.\n #\n+# November 2017\n+#\n+# Convert AVX512F+VL+BW code path to pure AVX512F, so that it can be\n+# executed even on Knights Landing. Trigger for modification was\n+# observation that AVX512 code paths can negatively affect overall\n+# Skylake-X system performance. Since we are likely to suppress\n+# AVX512F capability flag [at least on Skylake-X], conversion serves\n+# as kind of \u0022investment protection\u0022. Note that next *lake processor,\n+# Cannolake, has AVX512IFMA code path to execute...\n+#\n # Numbers are cycles per processed byte with poly1305_blocks alone,\n # measured with rdtsc at fixed clock frequency.\n #\n@@ -35,7 +45,7 @@\n # Haswell\t1.14/+175%\t1.11\t\t0.65\n # Skylake[-X]\t1.13/+120%\t0.96\t\t0.51\t[0.35]\n # Silvermont\t2.83/+95%\t-\n-# Knights L\t3.60/-\t\t1.65\t\t1.10\t(***)\n+# Knights L\t3.60/?\t\t1.65\t\t1.10\t?\n # Goldmont\t1.70/+180%\t-\n # VIA Nano\t1.82/+150%\t-\n # Sledgehammer\t1.38/+160%\t-\n@@ -50,8 +60,6 @@\n #\tCore processors, 50-30%, less newer processor is, but slower on\n #\tcontemporary ones, for example almost 2x slower on Atom, and as\n #\tformer are naturally disappearing, SSE2 is deemed unnecessary;\n-# (***)\tCurrent AVX-512 code requires BW and VL extensions and can not\n-#\texecute on Knights Landing;\n \n $flavour \u003d shift;\n $output \u003d shift;\n@@ -1685,7 +1693,6 @@ poly1305_blocks_avx2:\n .Leven_avx2:\n .cfi_startproc\n \tmov\t\tOPENSSL_ia32cap_P+8(%rip),%r10d\n-\tmov\t\t\u005c$`(1\u003c\u003c31|1\u003c\u003c30|1\u003c\u003c16)`,%r11d\n \tvmovd\t\t4*0($ctx),%x#$H0\t# load hash value base 2^26\n \tvmovd\t\t4*1($ctx),%x#$H1\n \tvmovd\t\t4*2($ctx),%x#$H2\n@@ -1698,8 +1705,8 @@ $code.\u003d\u003c\u003c___\t\tif ($avx\u003e2);\n \tcmp\t\t\u005c$512,$len\n \tjb\t\t.Lskip_avx512\n \tand\t\t%r11d,%r10d\n-\tcmp\t\t%r11d,%r10d\t\t# check for AVX512F+BW+VL\n-\tje\t\t.Lblocks_avx512\n+\ttest\t\t\u005c$`1\u003c\u003c16`,%r10d\t\t# check for AVX512F\n+\tjnz\t\t.Lblocks_avx512\n .Lskip_avx512:\n ___\n $code.\u003d\u003c\u003c___\tif (!$win64);\n@@ -2109,10 +2116,14 @@ if ($avx\u003e2) {\n # reason stack layout is kept identical to poly1305_blocks_avx2. If not\n # for this tail, we wouldn't have to even allocate stack frame...\n \n-my ($R0,$R1,$R2,$R3,$R4, $S1,$S2,$S3,$S4) \u003d map(\u0022%ymm$_\u0022,(16..24));\n-my ($M0,$M1,$M2,$M3,$M4) \u003d map(\u0022%ymm$_\u0022,(25..29));\n+my ($R0,$R1,$R2,$R3,$R4, $S1,$S2,$S3,$S4) \u003d map(\u0022%zmm$_\u0022,(16..24));\n+my ($M0,$M1,$M2,$M3,$M4) \u003d map(\u0022%zmm$_\u0022,(25..29));\n my $PADBIT\u003d\u0022%zmm30\u0022;\n-my $GATHER\u003d\u0022%ymm31\u0022;\n+\n+map(s/%y/%z/,($T4,$T0,$T1,$T2,$T3));\t\t# switch to %zmm domain\n+map(s/%y/%z/,($D0,$D1,$D2,$D3,$D4));\n+map(s/%y/%z/,($H0,$H1,$H2,$H3,$H4));\n+map(s/%y/%z/,($MASK));\n \n $code.\u003d\u003c\u003c___;\n .type\tpoly1305_blocks_avx512,\u005c@function,4\n@@ -2120,7 +2131,8 @@ $code.\u003d\u003c\u003c___;\n poly1305_blocks_avx512:\n .cfi_startproc\n .Lblocks_avx512:\n-\tvzeroupper\n+\tmov\t\t\u005c$15,%eax\n+\tkmovw\t\t%eax,%k2\n ___\n $code.\u003d\u003c\u003c___\tif (!$win64);\n \tlea\t\t-8(%rsp),%r11\n@@ -2133,52 +2145,53 @@ $code.\u003d\u003c\u003c___\tif ($win64);\n \tvmovdqa\t\t%xmm6,0x50(%r11)\n \tvmovdqa\t\t%xmm7,0x60(%r11)\n \tvmovdqa\t\t%xmm8,0x70(%r11)\n-\tvmovdqa32\t%xmm9,0x80(%r11)\n-\tvmovdqa32\t%xmm10,0x90(%r11)\n-\tvmovdqa32\t%xmm11,0xa0(%r11)\n-\tvmovdqa32\t%xmm12,0xb0(%r11)\n-\tvmovdqa32\t%xmm13,0xc0(%r11)\n-\tvmovdqa32\t%xmm14,0xd0(%r11)\n-\tvmovdqa32\t%xmm15,0xe0(%r11)\n+\tvmovdqa\t\t%xmm9,0x80(%r11)\n+\tvmovdqa\t\t%xmm10,0x90(%r11)\n+\tvmovdqa\t\t%xmm11,0xa0(%r11)\n+\tvmovdqa\t\t%xmm12,0xb0(%r11)\n+\tvmovdqa\t\t%xmm13,0xc0(%r11)\n+\tvmovdqa\t\t%xmm14,0xd0(%r11)\n+\tvmovdqa\t\t%xmm15,0xe0(%r11)\n .Ldo_avx512_body:\n ___\n $code.\u003d\u003c\u003c___;\n \tlea\t\t.Lconst(%rip),%rcx\n \tlea\t\t48+64($ctx),$ctx\t# size optimization\n-\tvmovdqa\t\t96(%rcx),$T2\t\t# .Lpermd_avx2\n+\tvmovdqa\t\t96(%rcx),%y#$T2\t\t# .Lpermd_avx2\n \n \t# expand pre-calculated table\n-\tvmovdqu32\t`16*0-64`($ctx),%x#$R0\n+\tvmovdqu32\t`16*0-64`($ctx),${R0}{%k2}{z}\n \tand\t\t\u005c$-512,%rsp\n-\tvmovdqu32\t`16*1-64`($ctx),%x#$R1\n-\tvmovdqu32\t`16*2-64`($ctx),%x#$S1\n-\tvmovdqu32\t`16*3-64`($ctx),%x#$R2\n-\tvmovdqu32\t`16*4-64`($ctx),%x#$S2\n-\tvmovdqu32\t`16*5-64`($ctx),%x#$R3\n-\tvmovdqu32\t`16*6-64`($ctx),%x#$S3\n-\tvmovdqu32\t`16*7-64`($ctx),%x#$R4\n-\tvmovdqu32\t`16*8-64`($ctx),%x#$S4\n+\tvmovdqu32\t`16*1-64`($ctx),${R1}{%k2}{z}\n+\tmov\t\t\u005c$0x20,%rax\n+\tvmovdqu32\t`16*2-64`($ctx),${S1}{%k2}{z}\n+\tvmovdqu32\t`16*3-64`($ctx),${R2}{%k2}{z}\n+\tvmovdqu32\t`16*4-64`($ctx),${S2}{%k2}{z}\n+\tvmovdqu32\t`16*5-64`($ctx),${R3}{%k2}{z}\n+\tvmovdqu32\t`16*6-64`($ctx),${S3}{%k2}{z}\n+\tvmovdqu32\t`16*7-64`($ctx),${R4}{%k2}{z}\n+\tvmovdqu32\t`16*8-64`($ctx),${S4}{%k2}{z}\n \tvpermd\t\t$R0,$T2,$R0\t\t# 00003412 -\u003e 14243444\n-\tvmovdqa64\t64(%rcx),$MASK\t\t# .Lmask26\n+\tvpbroadcastq\t64(%rcx),$MASK\t\t# .Lmask26\n \tvpermd\t\t$R1,$T2,$R1\n \tvpermd\t\t$S1,$T2,$S1\n \tvpermd\t\t$R2,$T2,$R2\n-\tvmovdqa32\t$R0,0x00(%rsp)\t\t# save in case $len%128 !\u003d 0\n+\tvmovdqa64\t$R0,0x00(%rsp){%k2}\t# save in case $len%128 !\u003d 0\n \t vpsrlq\t\t\u005c$32,$R0,$T0\t\t# 14243444 -\u003e 01020304\n \tvpermd\t\t$S2,$T2,$S2\n-\tvmovdqa32\t$R1,0x20(%rsp)\n+\tvmovdqu64\t$R1,0x00(%rsp,%rax){%k2}\n \t vpsrlq\t\t\u005c$32,$R1,$T1\n \tvpermd\t\t$R3,$T2,$R3\n-\tvmovdqa32\t$S1,0x40(%rsp)\n+\tvmovdqa64\t$S1,0x40(%rsp){%k2}\n \tvpermd\t\t$S3,$T2,$S3\n \tvpermd\t\t$R4,$T2,$R4\n-\tvmovdqa32\t$R2,0x60(%rsp)\n+\tvmovdqu64\t$R2,0x40(%rsp,%rax){%k2}\n \tvpermd\t\t$S4,$T2,$S4\n-\tvmovdqa32\t$S2,0x80(%rsp)\n-\tvmovdqa32\t$R3,0xa0(%rsp)\n-\tvmovdqa32\t$S3,0xc0(%rsp)\n-\tvmovdqa32\t$R4,0xe0(%rsp)\n-\tvmovdqa32\t$S4,0x100(%rsp)\n+\tvmovdqa64\t$S2,0x80(%rsp){%k2}\n+\tvmovdqu64\t$R3,0x80(%rsp,%rax){%k2}\n+\tvmovdqa64\t$S3,0xc0(%rsp){%k2}\n+\tvmovdqu64\t$R4,0xc0(%rsp,%rax){%k2}\n+\tvmovdqa64\t$S4,0x100(%rsp){%k2}\n \n \t################################################################\n \t# calculate 5th through 8th powers of the key\n@@ -2282,14 +2295,6 @@ $code.\u003d\u003c\u003c___;\n \tvpandq\t\t$MASK,$D3,$D3\n \tvpaddq\t\t$M3,$D4,$D4\t\t# d3 -\u003e d4\n \n-___\n-map(s/%y/%z/,($T4,$T0,$T1,$T2,$T3));\t\t# switch to %zmm domain\n-map(s/%y/%z/,($M4,$M0,$M1,$M2,$M3));\n-map(s/%y/%z/,($D0,$D1,$D2,$D3,$D4));\n-map(s/%y/%z/,($R0,$R1,$R2,$R3,$R4, $S1,$S2,$S3,$S4));\n-map(s/%y/%z/,($H0,$H1,$H2,$H3,$H4));\n-map(s/%y/%z/,($MASK));\n-$code.\u003d\u003c\u003c___;\n \t################################################################\n \t# at this point we have 14243444 in $R0-$S4 and 05060708 in\n \t# $D0-$D4, ...\n@@ -2327,7 +2332,6 @@ $code.\u003d\u003c\u003c___;\n \tvpaddd\t\t$R3,$S3,$S3\n \tvpaddd\t\t$R4,$S4,$S4\n \n-\tvpbroadcastq\t%x#$MASK,$MASK\n \tvpbroadcastq\t32(%rcx),$PADBIT\t# .L129\n \n \tvpsrlq\t\t\u005c$52,$T0,$T2\t\t# splat input\n@@ -2345,7 +2349,7 @@ $code.\u003d\u003c\u003c___;\n \tvpaddq\t\t$H2,$T2,$H2\t\t# accumulate input\n \tsub\t\t\u005c$192,$len\n \tjbe\t\t.Ltail_avx512\n-\t#jmp\t\t.Loop_avx512\n+\tjmp\t\t.Loop_avx512\n \n .align\t32\n .Loop_avx512:\n@@ -2532,7 +2536,7 @@ $code.\u003d\u003c\u003c___;\n \t vpaddq\t\t$H3,$T3,$H3\n \t vpaddq\t\t$H4,$T4,$H4\n \n-\t vmovdqu64\t16*0($inp),%x#$T0\n+\t vmovdqu\t16*0($inp),%x#$T0\n \tvpmuludq\t$H0,$R3,$M3\n \tvpmuludq\t$H0,$R4,$M4\n \tvpmuludq\t$H0,$R0,$M0\n@@ -2542,7 +2546,7 @@ $code.\u003d\u003c\u003c___;\n \tvpaddq\t\t$M0,$D0,$D0\t\t# d0 +\u003d h0*r0\n \tvpaddq\t\t$M1,$D1,$D1\t\t# d1 +\u003d h0*r1\n \n-\t vmovdqu64\t16*1($inp),%x#$T1\n+\t vmovdqu\t16*1($inp),%x#$T1\n \tvpmuludq\t$H1,$R2,$M3\n \tvpmuludq\t$H1,$R3,$M4\n \tvpmuludq\t$H1,$S4,$M0\n@@ -2552,7 +2556,7 @@ $code.\u003d\u003c\u003c___;\n \tvpaddq\t\t$M0,$D0,$D0\t\t# d0 +\u003d h1*s4\n \tvpaddq\t\t$M2,$D2,$D2\t\t# d2 +\u003d h0*r2\n \n-\t vinserti64x2\t\u005c$1,16*2($inp),$T0,$T0\n+\t vinserti128\t\u005c$1,16*2($inp),%y#$T0,%y#$T0\n \tvpmuludq\t$H3,$R0,$M3\n \tvpmuludq\t$H3,$R1,$M4\n \tvpmuludq\t$H1,$R0,$M1\n@@ -2562,7 +2566,7 @@ $code.\u003d\u003c\u003c___;\n \tvpaddq\t\t$M1,$D1,$D1\t\t# d1 +\u003d h1*r0\n \tvpaddq\t\t$M2,$D2,$D2\t\t# d2 +\u003d h1*r1\n \n-\t vinserti64x2\t\u005c$1,16*3($inp),$T1,$T1\n+\t vinserti128\t\u005c$1,16*3($inp),%y#$T1,%y#$T1\n \tvpmuludq\t$H4,$S4,$M3\n \tvpmuludq\t$H4,$R0,$M4\n \tvpmuludq\t$H3,$S2,$M0\n@@ -2585,11 +2589,11 @@ $code.\u003d\u003c\u003c___;\n \t# horizontal addition\n \n \tmov\t\t\u005c$1,%eax\n-\tvpsrldq\t\t\u005c$8,$H3,$D3\n-\tvpsrldq\t\t\u005c$8,$D4,$H4\n-\tvpsrldq\t\t\u005c$8,$H0,$D0\n-\tvpsrldq\t\t\u005c$8,$H1,$D1\n-\tvpsrldq\t\t\u005c$8,$H2,$D2\n+\tvpermq\t\t\u005c$0xb1,$H3,$D3\n+\tvpermq\t\t\u005c$0xb1,$D4,$H4\n+\tvpermq\t\t\u005c$0xb1,$H0,$D0\n+\tvpermq\t\t\u005c$0xb1,$H1,$D1\n+\tvpermq\t\t\u005c$0xb1,$H2,$D2\n \tvpaddq\t\t$D3,$H3,$H3\n \tvpaddq\t\t$D4,$H4,$H4\n \tvpaddq\t\t$D0,$H0,$H0\n@@ -2626,23 +2630,23 @@ $code.\u003d\u003c\u003c___;\n \t# lazy reduction (interleaved with input splat)\n \n \tvpsrlq\t\t\u005c$26,$H3,$D3\n-\tvpandq\t\t$MASK,$H3,$H3\n+\tvpand\t\t$MASK,$H3,$H3\n \t vpsrldq\t\u005c$6,$T0,$T2\t\t# splat input\n \t vpsrldq\t\u005c$6,$T1,$T3\n \t vpunpckhqdq\t$T1,$T0,$T4\t\t# 4\n \tvpaddq\t\t$D3,$H4,$H4\t\t# h3 -\u003e h4\n \n \tvpsrlq\t\t\u005c$26,$H0,$D0\n-\tvpandq\t\t$MASK,$H0,$H0\n+\tvpand\t\t$MASK,$H0,$H0\n \t vpunpcklqdq\t$T3,$T2,$T2\t\t# 2:3\n \t vpunpcklqdq\t$T1,$T0,$T0\t\t# 0:1\n \tvpaddq\t\t$D0,$H1,$H1\t\t# h0 -\u003e h1\n \n \tvpsrlq\t\t\u005c$26,$H4,$D4\n-\tvpandq\t\t$MASK,$H4,$H4\n+\tvpand\t\t$MASK,$H4,$H4\n \n \tvpsrlq\t\t\u005c$26,$H1,$D1\n-\tvpandq\t\t$MASK,$H1,$H1\n+\tvpand\t\t$MASK,$H1,$H1\n \t vpsrlq\t\t\u005c$30,$T2,$T3\n \t vpsrlq\t\t\u005c$4,$T2,$T2\n \tvpaddq\t\t$D1,$H2,$H2\t\t# h1 -\u003e h2\n@@ -2654,21 +2658,21 @@ $code.\u003d\u003c\u003c___;\n \tvpaddq\t\t$D4,$H0,$H0\t\t# h4 -\u003e h0\n \n \tvpsrlq\t\t\u005c$26,$H2,$D2\n-\tvpandq\t\t$MASK,$H2,$H2\n-\t vpandq\t\t$MASK,$T2,$T2\t\t# 2\n-\t vpandq\t\t$MASK,$T0,$T0\t\t# 0\n+\tvpand\t\t$MASK,$H2,$H2\n+\t vpand\t\t$MASK,$T2,$T2\t\t# 2\n+\t vpand\t\t$MASK,$T0,$T0\t\t# 0\n \tvpaddq\t\t$D2,$H3,$H3\t\t# h2 -\u003e h3\n \n \tvpsrlq\t\t\u005c$26,$H0,$D0\n-\tvpandq\t\t$MASK,$H0,$H0\n+\tvpand\t\t$MASK,$H0,$H0\n \t vpaddq\t\t$H2,$T2,$H2\t\t# accumulate input for .Ltail_avx2\n-\t vpandq\t\t$MASK,$T1,$T1\t\t# 1\n+\t vpand\t\t$MASK,$T1,$T1\t\t# 1\n \tvpaddq\t\t$D0,$H1,$H1\t\t# h0 -\u003e h1\n \n \tvpsrlq\t\t\u005c$26,$H3,$D3\n-\tvpandq\t\t$MASK,$H3,$H3\n-\t vpandq\t\t$MASK,$T3,$T3\t\t# 3\n-\t vporq\t\t$PADBIT,$T4,$T4\t\t# padbit, yes, always\n+\tvpand\t\t$MASK,$H3,$H3\n+\t vpand\t\t$MASK,$T3,$T3\t\t# 3\n+\t vpor\t\t32(%rcx),$T4,$T4\t# padbit, yes, always\n \tvpaddq\t\t$D3,$H4,$H4\t\t# h3 -\u003e h4\n \n \tlea\t\t0x90(%rsp),%rax\t\t# size optimization for .Ltail_avx2\n","s":{"c":1752937081,"u": 37138}}
],"g": 2142,"chitpc": 0,"ehitpc": 0,"indexed":0
,
"ab": 0, "si": 0, "db":0, "di":0, "sat":0, "lfc": "7d0a"}